Electrical components, for example, resistors, transistors, and capacitors, are commonly mounted on circuit panel structures such as printed circuit boards. Circuit panels ordinarily include a generally flat sheet of dielectric material with electrical conductors disposed on a major, flat surface of the sheet, or on both major surfaces. The conductors are commonly formed from metallic materials such as copper and serve to interconnect the electrical components mounted to the board. Where the conductors are disposed on both major surfaces of the panel, the panel may have via conductors extending through holes (or “through vias”) in the dielectric layer so as to interconnect the conductors on opposite surfaces. Multi-layer circuit panel assemblies have been made heretofore which incorporate multiple stacked circuit panels with additional layers of dielectric materials separating the conductors on mutually facing surfaces of adjacent panels in the stack. These multi-layer assemblies ordinarily incorporate interconnections extending between the conductors on the various circuit panels in the stack as necessary to provide the required electrical interconnections.
In microelectronic circuit packages, circuits and units are prepared in packaging levels of increasing scale. Generally, the smallest scale packaging levels are typically semiconductor chips housing multiple microcircuits and/or other components. Such chips are usually made from ceramics, silicon, and the like. Intermediate package levels (i.e., “chip carriers”) comprising multi-layer substrates may have attached thereto a plurality of small-scale chips housing many microelectronic circuits. Likewise, these intermediate package levels themselves can be attached to larger scale circuit cards, motherboards, and the like. The intermediate package levels serve several purposes in the overall circuit assembly including structural support, transitional integration of the smaller scale microcircuits and circuits to larger scale boards, and the dissipation of heat from the circuit assembly. Substrates used in conventional intermediate package levels have included a variety of materials, for example, ceramic, fiberglass reinforced polyepoxides, and polyimides.
The aforementioned substrates, while offering sufficient rigidity to provide structural support to the circuit assembly, typically have thermal coefficients of expansion much different than that of the microelectronic chips being attached thereto. As a result, failure of the circuit assembly after repeated use is a risk due to failure of adhesive joints between the layers of the assembly.
Likewise, dielectric materials used on the substrates must meet several requirements, including conformality, flame resistance, and compatible thermal expansion properties. Conventional dielectric materials include, for example, polyimides, polyepoxides, phenolics, and fluorocarbons. These polymeric dielectrics typically have thermal coefficients of expansion much higher than that of the adjacent layers.
There has been an increasing need for circuit panel structures, which provide high density, complex interconnections. Such a need can be addressed by multi-layer circuit panel structures; however, the fabrication of such multi-layer circuit assemblies has presented serious drawbacks. A common difficulty in manufacture is the alignment of holes and vias by drilling of the dielectric layers as increasing layers of circuitry are applied. Laser drilling is the most common method for forming vias, which can add significant cost to the manufacture of such circuit assemblies.
Generally multi-layer panels are made by providing individual, dual sided circuit panels with appropriate conductors thereon. The panels are then laminated one atop the other with one or more layers of uncured or partially cured dielectric material, commonly referred to as “prepregs” disposed between each pair of adjacent panels. Such a stack ordinarily is cured under heat and pressure to form a unitary mass. After curing, holes typically are drilled through the stack at locations where electrical connections between different boards are desired. The resulting holes or “through vias” are then coated or filled with electrically conductive materials usually by plating the interiors of the holes to form a plated through via. It is difficult to drill holes with a high ratio of depth to diameter, thus the holes used in such assemblies must be relatively large and consume a great deal of space in the assembly.
In applications wherein circuit layers are built one on top of another, a dielectric material typically separates the circuitized layers. Polymeric dielectric materials that typically are used in circuit assembly manufacture are thermoplastic or thermoset polymers. Thermoset materials are typically cured first to form a conformal coating. Although the conformally coated substrate may contain through holes conforming to a perforate substrate, blind vias are typically formed by drilling, such as by a laser.
U.S. Pat. No. 6,266,874 B1 discloses of method of making a microelectronic component by providing a conductive substrate or “core”; providing a resist at selected locations on the conductive core; and electrophoretically depositing an uncured dielectric material on the conductive core except at locations covered by the resist. The reference suggests that the electrophoretically deposited material can be a cationic acrylic- or cationic epoxy-based composition as those known in the art and commercially available. The electrophoretically deposited material then is cured to form a conformal dielectric layer, and the resist is removed so that the dielectric layer has openings extending to the conductive core at locations that had been covered by the resist. The holes thus formed and extending to the coated substrate or “core” are commonly referred to as “blind vias”. In one embodiment, the structural conductive element is a metal sheet containing continuous through holes or “through vias” extending from one major surface to the opposite major surface. When the dielectric material is applied electrophoretically, the dielectric material is deposited at a uniform thickness onto the conductive element surface and the hole walls. It has been found, however, that the electrophoretically deposited dielectric materials suggested by this reference can be flammable, and thus do not meet typical flame retardancy requirements. In addition, the method cannot be utilized on subsequent circuitized layers.
U.S. Pat. Nos. 5,224,265 and 5,232,548 disclose methods of fabricating multi-layer thin-film wiring structures for use in circuit assemblies. The dielectric applied to the core substrate preferably is a fully cured and annealed thermoplastic polymer such as polytetrafluoroethylene, polysulfone, or polyimide-siloxane, preferably applied by lamination.
U.S. Pat. No. 5,153,986 discloses a method of fabricating metal core layers for a multi-layer circuit board. Suitable dielectrics include thermally processable vapor-depositable conformal polymeric coatings. The method uses perforate metal cores providing coated through holes, however the thermally processable polymers are cured before laser drilling to form blind vias.
European Publication No. EP 0 573 053 describes a photocurable and thermosetting coating composition and a method for formation of a solder resist pattern using the composition. The water soluble composition comprises and epoxy resin comprising tertiary amine groups solubilized with a carboxylic acid, as well as photoreactive ethylenically unsaturated groups. The composition is applied to a printed circuit board and dried, thus reacting the solubilizing carboxylic acid with part of the epoxy groups. The coating is then exposed to actinic radiation through a photomask. Exposed portions are rendered insoluble and the remaining coating is dissolved away by dilute acid solution. The remaining pattern is then thermally cured, thus reacting the amine with the remaining epoxy groups. This method, however, is limited to a very specific group of amine-functional epoxy polymers.
U.S. Published Patent Application No. US 2002/0004982 A1 describes a method for forming blind vias without producing “haloing” in the underlying conductive layer. The method comprises applying an insulating layer onto one major surface of a substrate, providing holes in the insulating layer to the substrate, and then thermally curing the insulating layer. Holes are formed by either photo-etching or laser drilling. After the heat oxidized metal is reduced, the process is repeated on the other major surface. In the production of multi-layered double sided wiring boards, production efficiency is critical to be competitive in the marketplace. Sequential treatment of the major surfaces effectively doubles the number of steps in production, thereby reducing efficiency and yield.
Circuitization of intermediate package levels is conventionally performed by applying a positive- or negative-acting photoresist (hereinafter collectively referred to as “resist”) to the metallized substrate, followed by exposure, development, etching, and stripping to yield a desired circuit pattern. Resist compositions typically are applied, for example, by laminating, spin coating, electrodeposition, roll coating, screen printing, curtain or immersion techniques. The resist layer thus applied can have a thickness of 5 to 50 microns.
In addition to the substrates previously mentioned, conventional substrates for intermediate package levels can further include solid metal sheets such as those disclosed in U.S. Pat. No. 5,153,986. These solid structures must be perforated during fabrication of the circuit assembly to provide through vias for alignment purposes.
In view of the prior art processes, there remains a need in the art for multi-layer circuit panel structures which provide high density and complex interconnections, the fabrication of which overcomes the drawbacks of the prior art circuit assemblies.